FIG. 1 illustrates several types of conventional memory modules including single in-line memory modules (SIMM) and dual in-line memory modules (DIMM). SIMMs have memory chips on one side of the memory module, wherein DIMMs have memory chips on both sides of the memory module. DIMMs may further be defined as registered DIMMs (R-DIMM) and fully buffered DIMMs (FBDIMM).
In an R-DIMM, signals except data signals are transferred from a memory controller to the memory chips, via one or more registers. In a FBDIMM, all signals from a memory controller are passed to the memory chips through a hub or advanced memory buffer (AMB). As shown in FIG. 1, FBDIMMs may be advantageous for higher speed and/or higher density applications.
FIG. 2 illustrates a conventional FBDIMM including a hub and a plurality of memory chips. A hub may receive a southbound (SB) packet from a memory controller or an adjacent FBDIMM at receiver R and transmit the SB packet to an adjacent FBDIMM via a transmitter T. The hub may also receive a northbound packet (NB) from an adjacent FBDIMM and transmit it to the memory controller or an adjacent FBDIMM using a receiver R and transmitter T, from the opposite direction. A hub may provide clock (CLK) signals, control (CON) signals, and/or address (ADDR) signals to the plurality of memory chips. A hub may exchange data (DATA) back and forth between the plurality of memory chips.
FIG. 3 illustrates a conventional memory system including a host (for example, a memory controller) and a plurality of memory modules. CLK signals, southbound signals (STx) and northbound signals (NRx) are illustrated consistent with FIG. 2. A conventional memory system, such as the memory system illustrated in FIG. 3, may include FBDIMMs.
FIG. 4 illustrates a conventional memory system, such as the conventional memory system of FIG. 3 from a different perspective. The eight (8) memory modules (for example, FBDIMMs) of FIG. 4 are said to be connected in a “daisy chain” connection, wherein the plurality of memory modules are serially connected by a daisy chain bus. In such an arrangement, signals to and from the memory controller are transferred to each adjacent memory module in order.
FIG. 5 illustrates a conventional memory system in more detail. As shown in FIG. 5, the host (for example, a memory controller) includes a transmitter STx which transmits southbound packets (for example, high speed southbound packets) to a first FBDIMM MM1 and a receiver NRx, which receives northbound packets from the first FBDIMM MM1. A southbound packet may include FBDIMM selection bits, rank selection bits, control signals, address signals, and/or data to be written. Northbound packet may include data read from one of the plurality of FBDIMMs MM1-MMn. Each of the plurality of FBDIMMs (MM1-MMn) may include a hub, as shown in FIGS. 2-4. In addition to a hub, each of the plurality of FBDIMMs (MM1-MMn) may also include a plurality of memory devices M1-Mn, which receives memory information and execute read or write operations in accordance with the memory information.
As shown in FIG. 5, a hub may further include a southbound receiver SRx, a southbound transmitter STx, a northbound receiver NRx, a northbound transmitter NTx, and a control circuit. A southbound receiver (STx) receives a southbound packet from a first (or memory controller) or adjacent FBDIMM. A southbound transmitter STx transmits the southbound packet to an adjacent FBDIMM (except the last hub in the daisy chain).
The control circuit may decode a southbound packet into memory information which may include, for example, FBDIMM selection bits, rank selection bits, control signals, address signals, and/or data signals. The control signals may include /CS, /RAS, /CAS, and /WE, for example.
The control circuit may supply the memory information to a memory interface, memory register, or memory interface register, such as the DRAM interface DRAM IF shown in FIG. 5 (if the memory chips M1-Mn are DRAM memories). The memory interface, memory register, or memory interface register, such as the DRAM interface DRAM IF, receives the memory information and transfers the memory information to the plurality of memory devices M1-Mn.
The control circuit may also encode read data from plurality of memory devices M1-M2 via the memory interface, memory register, or memory interface register into packet format.
The northbound receiver NRx of each hub (except the last hub in the daisy chain) may receive northbound packets from an adjacent FBDIMM and the northbound transmitter NTx may transmit received northbound packets to the host (or memory controller) or adjacent FBDIMM.
FIG. 6A illustrates an example, conventional southbound (SB) packet format. As shown in FIG. 5, a southbound packet is transferred in a direction away from the host. The SB packet may include 10 bits and each bit may toggle 12 times in one cycle of a memory clock, as shown in FIG. 6A. The first four toggles, represented by “A” in FIG. 6A may contain a cyclic redundancy check (CRC) code and a command (CMD)/address (ADDR) code. A CRC code is a signal that may be utilized for identifying an error in the transferred signals. The remaining toggles, represented by “B” may contain data to be written or other commands (CMD).
FIG. 6B illustrates an example, conventional northbound (NB) packet format. As shown in FIG. 5, a northbound packet is transferred in a direction toward the host. As shown in FIG. 6B, a northbound packet may include 14 bits each of which toggles 12 times in one cycle of a memory clock. The northbound packet may be divided into one or more read frames, for example, read frame 1 (RDF1) and read frame 2 (RDF2), as illustrated in FIG. 6B.
FIG. 6C illustrates an example relationship between a reference clock (CLK_REF), a memory clock (CLK_MEM), and a packet transition. As illustrated in the example of FIG. 6C, CLK_MEM has a frequency double the frequency of CLK_REF and there are 12 packet transitions in one cycle of CLK_MEM.
FIG. 6D illustrates an example FBDIMM southbound (SB) command decoding system, including several example commands that may be used to control a DRAM. As illustrated, FIG. 6D illustrates memory information decoded from a southbound packet. As shown in FIG. 6D, a southbound packet may include module selection bits, command bits, one or more rank selection bits and address information.
As shown in the example of FIG. 6D, bits 21-23 may be used to select one FBDIMM among the plurality of FBDIMMS and may be defined as module selection bits. As set forth above, conventional memory systems may include eight FBDIMMS. As a result, 3 bits (bits 21-23) are needed to identify a particular FBDIMM.
As shown in the example of FIG. 6D, bits 20-18 may be used to identify the desired command CMD that may be used to control the FBDIMM.
As indicated in the above example of FIG. 6D, a single bit (bit 17) may be used to select the rank of the selected FBDIMM. The rank is defined which side of the FBDIMM, the desired FBDIMM is on.
As shown in the example of FIG. 6D, bits 16-0 may be used to identify the bank and address of the desired memory.
FIG. 7 is a timing diagram that illustrates write and read operations of a southbound (SB) packet in the conventional system illustrated in FIG. 5. FIG. 7 illustrates the reference clock CLK_REF, the memory clock, CLK_MEM, SB packets, memory modules MM1-MMn, and northbound packets.
In the timing diagram shown in FIG. 7, for a write operation, the reference clock CLK_REF is transferred to the hub from a clock transfer line. As discussed above in conjunction with FIG. 6C, CLK_MEM may have a frequency double the frequency of CLK_REF and may be generated by a phase lock loop (PLL) within the hub.
The southbound SB packet to be written may be transferred to all FBDIMMs in one cycle of CLK_MEM through southbound transmitters STx and southbound receivers SRx. The received write SB packet may be decoded into memory information by each hub. As shown in FIG. 6D, the memory information may include module selection bits, which may be decoded by the hub to indicate that a particular memory module (for example memory module MM1) has been selected. The memory devices on the memory module MM1 execute a write operation in accordance with the memory information. All other memory modules MM2-MMn do not execute the write operation because they were not identified by the module selection bits.
As shown in FIG. 7, for a read operation, a read SB packet may also be transferred to all FBDIMMs in one cycle of CLK_MEM through southbound transmitters STx and southbound receivers SRx. The received read SB packet may also be decoded into memory information by each hub. As shown in FIG. 6D, the memory information may include module selection bits, which may be decoded by the hub to indicate that a particular memory module (for example memory module MM1) has been selected. The memory devices on the memory module MM1 execute a read operation in accordance with the memory information. In particular, read data is transferred from the memory devices of memory module MM1 to the hub of memory module MM1. The hub of memory module MM1 may then encode the read data into northbound packets and transmit the northbound packets to the host or memory controller via northbound transmitters NTx and northbound receivers NRx.
In conventional memory systems, such as the ones described above in conjunction with FIGS. 1-7, it may be advantageous to be able to determine whether each memory module MM1-MMn (for example, each FBDIMM) is operating properly or not. In the conventional memory system described above, including eight (8) FBDIMMs, in order to test each FBDIMM, it is necessary for the system to perform eight (8) write operations and eight (8) read operations. Further, as memories become more densely integrated, more FBDIMMs will be included, and therefore, even more write and read operations will become necessary.